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by LdB
Wed Nov 14, 2018 6:07 pm
Forum: Bare metal, Assembly language
Topic: USB peripherals in bare metal?
Replies: 11
Views: 1734

Re: USB peripherals in bare metal?

As bzt said it's on the GitHub site :-) Looking at your original post you said you wanted to mess around and understand interrupts. If you work your way thru the following samples you should get it all. 1.) The old blinking activity led every second or so is the easiest way to start https://github.c...
by LdB
Mon Nov 12, 2018 1:58 am
Forum: Bare metal, Assembly language
Topic: Able to get up only one core not others
Replies: 5
Views: 309

Re: Able to get up only one core not others

It's called prologue and epilogue which means your optimizer level is either not set or set at O1 Anything from O2 upwards sets the flag -fomit-frame-pointer which is all you really need -fomit-frame-pointer Don't keep the frame pointer in a register for functions that don't need one. This avoids th...
by LdB
Sun Nov 11, 2018 5:51 am
Forum: Bare metal, Assembly language
Topic: Able to get up only one core not others
Replies: 5
Views: 309

Re: Able to get up only one core not others

What you might want to try is slowing porting your code into my simple sample, as I have it working https://github.com/LdB-ECM/Raspberry-Pi/tree/master/Multicore Be pretty quick to work out the problem from there. My suggestion is just alter main.c to use my CoreExecute function (which in theory wor...
by LdB
Fri Nov 09, 2018 1:37 am
Forum: Bare metal, Assembly language
Topic: information of bcm2835 mailbox and doorbell
Replies: 5
Views: 284

Re: information of bcm2835 mailbox and doorbell

Careful there are two sets of mailboxes and doorbells, you would need to emulated both correctly The core mailboxes and doorbells are detailed in https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf The system has sixteen mailboxes, four for each core. The system has...
by LdB
Fri Nov 09, 2018 1:16 am
Forum: Bare metal, Assembly language
Topic: Able to get up only one core not others
Replies: 5
Views: 309

Re: Able to get up only one core not others

I am dubious about your core kick usually I would bind the sev into the last instruction before return in core_enable. So to mimic that behaviour at a guess try core_enable(1, &cOne ) ; asm volatile ("sev"); core_enable(2, &cTwo ) ; asm volatile ("sev"); core_enable(3, &cThree ) ; asm volatile ("sev...
by LdB
Thu Nov 08, 2018 1:23 pm
Forum: Bare metal, Assembly language
Topic: Problem with BCM2835 datasheet
Replies: 4
Views: 223

Re: Problem with BCM2835 datasheet

The above is correct it's listed on the error errata sheet, which used to be on the stickies not sure if it still is. Errata p24 : AUXSPI0/1_CNTL1 Register table, the bit numbering is wrong, it should be 31:11 p25 : AUXSPI0/1_STAT Register table 31:28 : TX FIFO Level (note that the maximum value is ...
by LdB
Mon Nov 05, 2018 4:01 pm
Forum: Bare metal, Assembly language
Topic: Optimizing data structures for NEON
Replies: 4
Views: 513

Re: Optimizing data structures for NEON

I didn't see this before but having played around with this a couple of weeks ago, you didn't mention a crucial thing. To get GCC to do it properly you need #include <arm_neon.h> That thing is a massive file and has all the shortcuts in it. It only does basic optimizations without it. I also found y...
by LdB
Tue Oct 30, 2018 1:00 pm
Forum: Bare metal, Assembly language
Topic: Pi 3B+ Activity LED
Replies: 18
Views: 3471

Re: Pi 3B+ Activity LED

Nope but it has a pretty obvious bug ... not 27 .. try 9 .. no idea where the 27's come from ra=GET32(GPFSEL2); ra&=~(7<<27); ra|=1<<27; PUT32(GPFSEL2,ra); Each GPFSEL covers 10 GPIO as they are 3 bits .. 10x3 = 30 bits of the 32 bit register .. look at datasheet GPFSEL0 = GPIO0 .. 9 GPFSEL1 = GPIO1...
by LdB
Sun Oct 28, 2018 4:11 pm
Forum: Bare metal, Assembly language
Topic: Masking Sync exceptions on PI3
Replies: 2
Views: 338

Re: Masking Sync exceptions on PI3

Don't play much with EL3 but AFAIK you make SMC calls in EL2/EL3 not usually SVC The manual says http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/ch10s02s04.html If you make an SVC call when in EL2 or EL3 it will still cause a synchronous exception at the same Exception level, an...
by LdB
Wed Oct 24, 2018 7:34 am
Forum: General programming discussion
Topic: VS17 Help
Replies: 34
Views: 4602

Re: VS17 Help

Same I can't be bothered scratching around with other IDE's but you just don't bring it up on this forum because it's linux centric. Having to try to justify why and get into the same stupid discussion is annoying.
by LdB
Mon Oct 22, 2018 2:58 am
Forum: Bare metal, Assembly language
Topic: Code between framebuffer and output?
Replies: 5
Views: 530

Re: Code between framebuffer and output?

I can't really work out what you are trying to do so I can only sparse comment. Typically on the VC4 you would do colorspace conversion by simply using a shader in the GL pipeline the destination a framebuffer the source whatever format your data is in. If you look at OpenGL there are a myriad of GL...
by LdB
Thu Oct 18, 2018 8:38 am
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

Good to hear :-) Remember when you do your threads you can remove the complex function pointer union because you will jump it to entry so you just need the address thru the mailbox. You can't ever return so there is no point using a function just use a 1 line asm with the address to jump it to the a...
by LdB
Thu Oct 18, 2018 2:29 am
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

Yes I would go down the pthreads path as a start for your 1st O/S it's the simplest, if you make it modular you can even have one system on each core. Then you can play with interconnecting the thread systems on each core or make the cores all work in one thread system. Pros and cons to that choice....
by LdB
Wed Oct 17, 2018 10:07 am
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

No .. you aren't getting it. You have the write address wrong (0x4000008C .. NOT 9c) think about the index after it but problem is deeper I dont even get what that function is for. But your code is structurally not doing what it has to .. so let me fix it There is a bit of an issue going on are you ...
by LdB
Wed Oct 17, 2018 8:30 am
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

That is the physical mailbox hardware between the cores .. you can use interrupts etc if you want remember this sheet for the hardware https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf 0x4000_00CC = Core 0 Mailbox 3 Rd/Clr 0x4000_00DC = Core 1 Mailbox 3 Rd/Clr 0x4...
by LdB
Wed Oct 17, 2018 7:02 am
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

I had a few misplaced ampersands doing the terminate, I found that when I tried to compile it :-) On the other yes you need to go to 2 clear steps and you need to stop trying to merge them 1.) Bring the MMU online on each core 2.) Then setup what you want to do with the cores after that. Currently y...
by LdB
Tue Oct 16, 2018 2:26 pm
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

UPDATE: Since I didn't have to change console.c I tested it with your console_print function ... works :-) https://github.com/LdB-ECM/Exchange/tree/master/Raspi3-Kernel-master Lets try a different version ... We change the function pointer static void (*Console_WriteChar) (char*) = NULL; // The out...
by LdB
Tue Oct 16, 2018 1:53 pm
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

It is trivial to do what you want ... I assume you can make a suitable function on console.c which matches my function I setup next. So make a suitable interface instead of the character by character say something like void console_print(char* buffer, int count); You will need a size you won't be ab...
by LdB
Tue Oct 16, 2018 12:42 am
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

Update at bottom: I will deal with that in a second but you also have a print instruction right after the MMU_init call which never appears. So we are left with even more questions about your printf implementation. You also have printf which uses a semaphore used in places that raised my eyebrows l...
by LdB
Mon Oct 15, 2018 1:21 pm
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

You have a semaphore lock on it so using dynamic memory just slows down your print function, you only ever need one buffer it is impossible you need more that semaphore enforces that. As a general rule you make it fixed size and flush at a fixed point. For example a typical implementation will flush...
by LdB
Mon Oct 15, 2018 9:58 am
Forum: Bare metal, Assembly language
Topic: Multicore Code works on QEMU not on real hardware
Replies: 19
Views: 1392

Re: Multicore Code works on QEMU not on real hardware

For a start you have bugs in the GPU mailbox messages. It's barely 100 lines of code in all the initialize code check them all .. I found 2 straight up Uart init the clock does not take 12 bytes it takes 8 you got it right in system.c but wrong in uart.c get_gpu_memory_split in gpu_memory.c, the res...
by LdB
Thu Oct 11, 2018 4:57 am
Forum: Bare metal, Assembly language
Topic: Accessing GPIO Pins via Bare Metal
Replies: 5
Views: 836

Re: Accessing GPIO Pins via Bare Metal

There is no logic behind the correlation the numbers you see in code are the GPIO numbers which is how they come in as registers. The physical is just how the board designer took them to a physical header if at all. So you end up with a mapping of GPIO numbers on physical pin numbers. They basically...
by LdB
Thu Oct 11, 2018 1:43 am
Forum: Bare metal, Assembly language
Topic: Arm Core Clock Speeds
Replies: 3
Views: 588

Re: Arm Core Clock Speeds

I don't think there is individual clocks. I imagine it would be far harder to synchronize a pile of different speed cores on the same physical bus to the shared resources. Easy to test change the speed on one core and read it on another you know how to run code on each core. I am guessing any core c...
by LdB
Wed Oct 10, 2018 1:32 am
Forum: Bare metal, Assembly language
Topic: Arm Core Clock Speeds
Replies: 3
Views: 588

Re: Arm Core Clock Speeds

Yes it was an error you spotted it earlier in another post and I agreed it should be if(mailbox_tag_message(&buffer[0], 5, MBOX_TAG_GET_MAX_CLKRATE, 8, 8, CLK_ARM_ID, 0)). https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=213514 What I also noticed earlier and commented on the Pi3 was when you...
by LdB
Tue Oct 09, 2018 2:55 am
Forum: Bare metal, Assembly language
Topic: Help With Simple Hello World Program in Bare Metal ASM
Replies: 4
Views: 621

Re: Help With Simple Hello World Program in Bare Metal ASM

Okay but isn't the address given the PL011 uart which will be going to the Wifi on the PiZeroW. I suspect the 16550 uart (0x20215040) will be the one acting as the kernel output. I use a few lines of assembler code to autodetect all this rubbish to avoid having to think about it but I was messing ar...

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