Go to advanced search

by deater
Sun Apr 22, 2018 6:50 pm
Forum: Bare metal, Assembly language
Topic: acking GPU interrupts
Replies: 1
Views: 611

acking GPU interrupts

On a Pi3 I occasionally get a GPU interrupt (bit 8 in the core interrupt sources as listed in the QA7 document). I'm pretty sure this is low-power related, as the interrupt happens at the same time the little lightning bolt appears on the HDMI display. Is there any way to get more info on the source...
by deater
Sat Apr 21, 2018 1:38 pm
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 3630

Re: multi-core shared memory communication

However I am pretty sure that my SCTLR register is coming up as 0xc50838 which has the caches disabled. Well it looks like I am wrong again. I forgot that when trying to get things working I had implemented the boot ordering described in the ``Bare-metal Boot Code for AMv8-A Processors'' document f...
by deater
Sat Apr 21, 2018 1:19 pm
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 3630

Re: multi-core shared memory communication

I have compared the referenced armstub7.S source code with the stub which is actually loaded on my RPi 3B with a firmware from Apr 9. I'm sure, it's the same here. Setting the data cache enable bit in the control register has no effect without enabling the MMU. I did read back the CPU Extended Cont...
by deater
Sat Apr 21, 2018 12:45 am
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 3630

Re: multi-core shared memory communication

Unless I am missing something, this can't be the stub that's booting on my machine as the stub turns on the I/D caches and on my machine they are definitely disabled at boot. Also I'm pretty sure I read out and test for the SMP bit and it isn't set. I think I found out the issue. And indeed the stu...
by deater
Fri Apr 20, 2018 11:14 pm
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 3630

Re: multi-core shared memory communication

The SMP bit is already set by the ARM stub, before your code is started, here: https://github.com/raspberrypi/tools/blob/master/armstubs/armstub7.S#L69 You do not need to touch it. There is only one exception: You use the "kernel_old=1" setting in config.txt. I don't have any kernel_old setting in ...
by deater
Thu Apr 19, 2018 5:20 pm
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 3630

Re: multi-core shared memory communication

Thanks, I was finally able to get core0 to see the writes by the other cores by invalidating the caches as you describe. I had to invalidate the entire L1 dcache, just invalidating the memory addresses of the shared data structure didn't seem to work. I take it back, flushing the data cache only se...
by deater
Tue Apr 17, 2018 4:53 am
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 3630

Re: multi-core shared memory communication

well even when the memory region is set to be shared and un-cached I did had the same issue that during the boot-up of the different cores the flag that a core is ready was not proper read by the other core. I've solved this by clearing/invalidating the cache in the core that has updated the flag a...
by deater
Sun Apr 15, 2018 3:07 pm
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 3630

Re: multi-core shared memory communication

In order to support cache coherence between cores you need to ensure that the page table entries contain the shared flag, you don't show the code you are using but normally this is done by setting the S bit in each entry. See the ARM Architecture Reference Manual for more information. I'm using 0x9...
by deater
Sat Apr 14, 2018 6:39 pm
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 3630

multi-core shared memory communication

I am writing bare-metal code (running on a pi3b but in 32-bit mode). I can successfully unpark the multiple cores and have them run, but I can't seem to get memory writes on one core to appear on the others. I enable the MMU and caches on all cores. I also enable the SMP bit in the AUX register (do ...
by deater
Wed Apr 11, 2018 6:19 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 3857

Re: [solved] RPi-3 (aarch32) - MMU activation hangs

sorry for the delay in replying. Using dcache clearing code seems to work fine for getting the GPU framebuffer to work. I was trying to use the same code for accessing the mailbox to get the current temperature, and no matter how I clear the caches I cannot get the temperature tags interface to work...
by deater
Fri Mar 30, 2018 11:39 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 3857

Re: [solved] RPi-3 (aarch32) - MMU activation hangs

This works for me on Pi1 systems, but on my Pi3 I can't seem to get it to work. What instructions are you using to flush the cache on the Pi3?
by deater
Thu Mar 29, 2018 12:17 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 3857

Re: [solved] RPi-3 (aarch32) - MMU activation hangs

I figured out my problem. Some executable code was exiting, and new executable code was being loaded into the same location (via the dcache) but the icache had the old version, causing the weird memory errors. I added an icache flush to the loading code and now everything works with caches enabled. ...
by deater
Sun Mar 25, 2018 5:11 am
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 3857

Re: [solved] RPi-3 (aarch32) - MMU activation hangs

I have to say this was a really timely thread, I've spent the past few days trying to get MMU memory protection going on the Pi3 using my OS (http://www.deater.net/weave/vmwprod/vmwos/). I never would have figured out the proper page table settings without this thread. On an added note, are caches w...
by deater
Fri Aug 18, 2017 9:18 pm
Forum: Bare metal, Assembly language
Topic: pi3 PMU interrupt settings
Replies: 6
Views: 2165

Re: pi3 PMU interrupt settings

Fine, let me rephrase it in a way that's also true. I have my own baremetal OS I am writing and I am trying to get the PMU to work. Does anyone know the proper PMU interrupt number/types for the Pi3? Ooh! Sneaky! I see what you did there. :D I do have such an OS, and it does have performance monito...
by deater
Tue Aug 15, 2017 8:06 pm
Forum: Bare metal, Assembly language
Topic: pi3 PMU interrupt settings
Replies: 6
Views: 2165

Re: pi3 PMU interrupt settings

The PMU interrupts appear in the local peripherals block on the Pi2 and Pi3, section 4.10 of the QA7 document shows it as bit 9 of the core Interrupt source registers. There is one register for each core but the layout is the same for all of them, in bare metal you'll need to invent some kind of nu...
by deater
Mon Aug 14, 2017 4:50 pm
Forum: Bare metal, Assembly language
Topic: pi3 PMU interrupt settings
Replies: 6
Views: 2165

Re: pi3 PMU interrupt settings

Fine, let me rephrase it in a way that's also true. I have my own baremetal OS I am writing and I am trying to get the PMU to work. Does anyone know the proper PMU interrupt number/types for the Pi3?
by deater
Mon Aug 14, 2017 4:04 pm
Forum: Bare metal, Assembly language
Topic: pi3 PMU interrupt settings
Replies: 6
Views: 2165

pi3 PMU interrupt settings

Hello I'm trying to get the hardware performance counters (PMU) going on 64-bit-pi3 with upstream Linux, which involves having the proper PMU Interrupt settings in the device-tree file. Is there documentation available on what these settings should be for pi3? For example, on a similar architecture ...
by deater
Mon May 16, 2016 7:21 pm
Forum: Bare metal, Assembly language
Topic: vmwOS bare metal operating system
Replies: 4
Views: 1491

Re: vmwOS bare metal operating system

I'm currently using the arm-none-eabi toolchain that you get when you run "apt-get install gcc-arm-none-eabi" on a debian unstable system. arm-none-eabi-gcc (15:4.9.3+svn231177-1) 4.9.3 20150529 (prerelease) It looks like the compile error is because the code is using "restrict" as a variable rather...
by deater
Mon May 16, 2016 2:32 am
Forum: Bare metal, Assembly language
Topic: vmwOS bare metal operating system
Replies: 4
Views: 1491

vmwOS bare metal operating system

I'm not sure if it will be of interest here, but I have a project that started out as some bare metal experiments and is gradually becoming more and more like a simple UNIX-like operating system. There's a website here: http://www.deater.net/weave/vmwprod/vmwos/ and all of the code is available for ...
by deater
Fri Mar 18, 2016 4:35 am
Forum: General discussion
Topic: Pi3 incorrect results under load (possibly heat related)
Replies: 105
Views: 52559

Re: Pi3 incorrect results under load (possibly heat related)

Would you mind humouring me, and recompile your OpenBLAS library and test again? Build OpenBLAS with "make TARGET=ARMV6 DYNAMIC_ARCH=0 USE_THREAD=1 USE_OPENMP=0". From multiple runs, do you still see any residual failures on Pi3B? What exactly are you getting at here? I've run this HPL/OpenBLAS com...
by deater
Tue Mar 15, 2016 8:11 pm
Forum: General discussion
Topic: Pi3 incorrect results under load (possibly heat related)
Replies: 105
Views: 52559

Re: Pi3 incorrect results under load (possibly heat related)

haha yes, but being an engineering professor doesn't necessarily make me a better tester. I'm one of those crazy people who makes large computing clusters out of the PIs, which is why I care about Linpack performance (Specifically GFLOPS/W). I can see how that's sort of outside the normal testing ar...
by deater
Tue Mar 15, 2016 7:25 pm
Forum: General discussion
Topic: Pi3 incorrect results under load (possibly heat related)
Replies: 105
Views: 52559

Re: Pi3 incorrect results under load (possibly heat related)

over_voltage=2 works on my board, I have done multiple linpack runs with N=10000 and they have finished properly.

I do have a small heatsink on the processor though.
by deater
Sun Mar 13, 2016 5:33 am
Forum: General discussion
Topic: Pi3 incorrect results under load (possibly heat related)
Replies: 105
Views: 52559

Re: Pi3 incorrect results under load (possibly heat related)

I just wanted to answer that yes, the hpl binary provided does run just fine on a pi2 with no problems (you can run it with N=10000 and it will still run). Currently only getting 1GFLOP out of it though, which is odd, because I know I've gotten 1.4GFLOP in the past. It's also nice to see that the pi...
by deater
Fri Mar 11, 2016 11:50 pm
Forum: General discussion
Topic: Pi3 incorrect results under load (possibly heat related)
Replies: 105
Views: 52559

Re: Pi3 incorrect results under load (possibly heat related)

I realize those directions are probably too hard. Alternately, you can install gfortran and libmpich-dev libs and then the following binary shoud work: http://web.eece.maine.edu/~vweaver/junk/pi3_hpl.tar.gz I have been having trouble isolating the problem, other than that N=8000 in the HPL.dat file ...
by deater
Fri Mar 11, 2016 9:58 pm
Forum: General discussion
Topic: Pi3 incorrect results under load (possibly heat related)
Replies: 105
Views: 52559

Re: Pi3 incorrect results under load (possibly heat related)

The setup is a bit involved. I run Linpack on all my machines (you can see a summary here http://web.eece.maine.edu/~vweaver/group/machines.html ) A quick runthrough on how I compile it can be found here, but just to warn you it takes a while to get it going. https://github.com/deater/performance_re...

Go to advanced search