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by AlfredJingle
Thu Aug 02, 2018 9:54 am
Forum: Bare metal, Assembly language
Topic: Gpio operation with a bare metal program - Why so slow?
Replies: 7
Views: 777

Re: Gpio operation with a bare metal program - Why so slow?

Probably rather a stupid question, but did you leave HYP-mode and start the MMU? If not than you will never reach Linux speeds.
by AlfredJingle
Sat Jul 21, 2018 12:23 pm
Forum: Bare metal, Assembly language
Topic: When compiling for Pi3 in Arch32 enabling VFP
Replies: 7
Views: 545

Re: When compiling for Pi3 in Arch32 enabling VFP

For what it is worth, I use:

Code: Select all

--no-warn -mcpu=cortex-a53+crc -mfpu=neon-vfpv4
which in my case ( I use as, not gcc ) works fine and only reports errors.
by AlfredJingle
Tue Jul 17, 2018 12:32 pm
Forum: Bare metal, Assembly language
Topic: Any tricks to further optimize this memory diffing code?
Replies: 4
Views: 444

Re: Any tricks to further optimize this memory diffing code?

I have presently no Pi-Zero running so these are partly theoretical musings. But I did a lot of optimizing on a pi1 and based on that the following: I would test if doing the actual comparison is faster with the following routine: sub r3, r3, r7 sub r4, r4, r8 sub r5, r5, r9 sub r6, r6, r10 orr r3, ...
by AlfredJingle
Sat Jun 23, 2018 8:41 pm
Forum: Bare metal, Assembly language
Topic: Writing to the framebuffer is slow
Replies: 19
Views: 1911

Re: Writing to the framebuffer is slow

You write to the virtual address. If you do a 1:1 mapping, as described above by LdB, there is no difference between physical and virtual addresses.
by AlfredJingle
Wed Jun 13, 2018 12:14 pm
Forum: Bare metal, Assembly language
Topic: multi-core shared memory communication
Replies: 15
Views: 2169

Re: multi-core shared memory communication

Hi ChrisYin The page-table-location is set per core, and so the page-table must not be the same for all cores. This can be used, for instance, to make sure that one core cannot see or overwrite the code from another core. This by having the different page-tables point to different parts of physical ...
by AlfredJingle
Wed Jun 13, 2018 10:39 am
Forum: Bare metal, Assembly language
Topic: Multi-core example fails on Pi3 B+, aarch32?
Replies: 12
Views: 765

Re: Multi-core example fails on Pi3 B+, aarch32?

As it happens, I have FPU-activation in front of me ( pi3 Aarch32 )

Code: Select all

		mov r0, #0xf00000		@ make cp10 en 11 fully accesible - pi3 - see page 4272 of ARMv8 trm
		mcr p15, 0, r0, c1, c0, 2	@ Write r0 to CPACR
		isb

		mov r1, #0x40000000		@ Set FPEXC_EN bit to enable the FPU
		vmsr FPEXC, r1
		isb
		
by AlfredJingle
Wed Jun 13, 2018 10:24 am
Forum: Bare metal, Assembly language
Topic: Writing to the framebuffer is slow
Replies: 19
Views: 1911

Re: Writing to the framebuffer is slow

Hi LizardLad: Yes once the translation tables are activated you can just write/read to/from any memory-location like you would normally, it just is much faster. In my system a fill of a 3Mb screen buffer takes between 3-5 ms. This variation in time comes from whether the GPU reads from vc-memory at ...
by AlfredJingle
Fri Apr 06, 2018 6:15 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 2448

Re: [solved] RPi-3 (aarch32) - MMU activation hangs

Hi, Yeah, I use that routine for cleaning of the datacaches as well. I adapted it a bit so that it takes as input which of the three principle cache-actions it has to perform: Namely either: mcr p15, 0, r11, c7, c6, 2 @ = DCISW - datacache invalidate by set/way or mcr p15, 0, r11, c7, c10, 2 @ = DCC...
by AlfredJingle
Tue Mar 20, 2018 7:33 pm
Forum: Bare metal, Assembly language
Topic: Pi 3B+ Activity LED
Replies: 16
Views: 2668

Re: Pi 3B+ Activity LED

Well, I had to wait till today to get my hands on one. I had no problems getting it to run at 1.5 Mhz and the boatloader of DWELCH works nicely. Things which I noticed as seemingly different are that I see a lot more noise created on the power-lines, and the colors created on the monitor (bare-metal...
by AlfredJingle
Sun Mar 18, 2018 1:55 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 2448

Re: RPi-3 (aarch32) - MMU activation hangs

Hi schnoogle, I re-checked my system and I have exactly the same entries in my translation-table and the source for disabling and setting the MMU is essentially the same. See below (prolog, next and ldv32 are small macro's handling popping, pushing of, and loading of immediates into registers and th...
by AlfredJingle
Sat Mar 17, 2018 10:36 am
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 2448

Re: RPi-3 (aarch32) - MMU activation hangs

Hi schnoogle, Aah, now we seem to be getting somwhere! Your translation-table as such seems to be correct (as far as I understand C...) but while setting the TTBR0 you ORR MMUtable with 0x406a. But the 0x406a already contains the translation-table address. The first 4 in 0x406a means that the transl...
by AlfredJingle
Thu Mar 15, 2018 7:41 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 2448

Re: RPi-3 (aarch32) - MMU activation hangs

What we haven’t discussed is the actual settings in the TLB and the memory attributes for the TTRB0. What actaul attributes did you use in the TLB and what memory attributes did you specify for TTRB0? Get these wrong or incompatible and the MMU will not start. I use 0x406A as memory attribute for TT...
by AlfredJingle
Tue Mar 06, 2018 12:58 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 2448

Re: RPi-3 (aarch32) - MMU activation hangs

I literally use the followoing code to switch on SMP: MRRC p15, 1, r0, r1, c15 orr r0, r0, #64 @ set bit [6] op 1 - this is the non-secure version!!!! @ the secure versie can only be done in MON=el3 MCRR p15, 1, r0, r1, c15 @ Write CPU Extended Control Register = ACTLR isb I do that well before sett...
by AlfredJingle
Sun Feb 25, 2018 11:26 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 2448

Re: RPi-3 (aarch32) - MMU activation hangs

I looked at your code and I have only two remarks: a). Did you set a stackpointer? If you switch from HYP to SYS, you have to again define your stack-pointer, as the registers are (partly) mode-specific. b). I first set the flags for I-cache and D-cache, and in a second action switch on the MMU. I d...
by AlfredJingle
Mon Feb 12, 2018 10:08 pm
Forum: Bare metal, Assembly language
Topic: Secure state and non secure state in Rpi3
Replies: 4
Views: 925

Re: Secure state and non secure state in Rpi3

You are the one setting and defining the handling of the secure and non-secure state. The whole TRUST-zone system seems to be a standard and very thorough way of doing just that, as it is not easy doing it fully correctly. But for your own stuff you can do whatever you want, and you can define what ...
by AlfredJingle
Mon Feb 12, 2018 9:52 pm
Forum: Bare metal, Assembly language
Topic: [solved] RPi-3 (aarch32) - MMU activation hangs
Replies: 23
Views: 2448

Re: RPi-3 (aarch32) - MMU activation hangs

Hi, Don't know if I can help you, but at least I see some issues. Maybe this helps. I only use assembly so you have to do the translation into C yourself. First: Coherency on a ARMv8 processor is not set using SMP but using the following code. MRRC p15, 1, r0, r1, c15 orr r0, r0, #64 @ set bit [6] o...
by AlfredJingle
Mon Jan 08, 2018 8:01 pm
Forum: Bare metal, Assembly language
Topic: Powering CPUs on/off in RPi3
Replies: 11
Views: 1663

Re: Powering CPUs on/off in RPi3

Haha, I know that feeling: I wanna do it because I wanna do it! For the past 3 years I have been busy developing a Raspberry based, OS-free, C-free, Library-free, Forth based home-computer (like the ones in the 80s - fast booting and lots of fun to use). And there is NO logic behind it that other th...
by AlfredJingle
Sun Jan 07, 2018 1:19 pm
Forum: Bare metal, Assembly language
Topic: problem switching on i2c0 - any ideas?
Replies: 1
Views: 358

Re: problem switching on i2c0 - any ideas?

Ooh never mind, I found the answer in these forums: i2c0 has been confiscated by the Raspberry Organisation somewhere in 2014. First to read an identifying eeprom during boot. This would have allowed to free ic20 after boot if no eeprom was found. But on the rPi3 it is also used for lots of other fu...
by AlfredJingle
Sun Jan 07, 2018 10:12 am
Forum: Bare metal, Assembly language
Topic: Powering CPUs on/off in RPi3
Replies: 11
Views: 1663

Re: Powering CPUs on/off in RPi3

Ooh, my mistake!

Out of curriosity: Why would you want to switch off any further than using wfi? Power consumption is very close to zero for a core that way.
by AlfredJingle
Sat Jan 06, 2018 5:55 pm
Forum: Bare metal, Assembly language
Topic: Powering CPUs on/off in RPi3
Replies: 11
Views: 1663

Re: Powering CPUs on/off in RPi3

Hi, In assembly you use the WFE command or WFI for that. They tell the Core to stop (as in don't do anything) and wait till either an Event or Interrupt happen (for definitions see the ARMv8 ref. manual). If you set the WFI in the interrupt handler of the Core it will always go back to nothing no ma...
by AlfredJingle
Sat Jan 06, 2018 5:42 pm
Forum: Bare metal, Assembly language
Topic: Dave Welche's bootloaders for RPi3 or other alternative
Replies: 18
Views: 2253

Re: Dave Welche's bootloaders for RPi3 or other alternative

Hi, One thing not yet mentioned is that on the Raspberry the clock of the mini-UART is dependant on the core-freq, (which is not the cpu-freq). On the pi1 and 2 the core-freq was always 250Mhz, even in Turbo-mode. On the 3 starting turbo-mode changes the core-frequency to 400Mhz, and thus a differen...
by AlfredJingle
Sat Jan 06, 2018 5:24 pm
Forum: Bare metal, Assembly language
Topic: Enabling MMU slows down VFP?
Replies: 5
Views: 744

Re: Enabling MMU slows down VFP?

Hi This is what I use: 0x90C0E for normal memory. (0x50C0E is fine in itself but means you use 16Mb sections which you must do consistently throughout.) Than 1 1Mb section with 0x90C12. This a uncached part of memory and is handy for Mailbox work. 0x90C1E for screen memory and 0x90C16 for everything...
by AlfredJingle
Sat Jan 06, 2018 4:13 pm
Forum: Bare metal, Assembly language
Topic: problem switching on i2c0 - any ideas?
Replies: 1
Views: 358

problem switching on i2c0 - any ideas?

Hi, Has anybody here had succes with the switching on of the bsc0 controller on a Raspberry 3 in assembly? On my OS-free baremetal system in Arch32, I want to use i2c0 on pins 27 and 28 and I fail miserably. I have no problem setting up the bsc1 controller (sda1 and scl1 on pins 3 and 5) and contact...
by AlfredJingle
Sat Jan 06, 2018 3:54 pm
Forum: Bare metal, Assembly language
Topic: Problem connecting Rpi Zero as I2C master to Arduino Uno as I2C slave
Replies: 2
Views: 800

Re: Problem connecting Rpi Zero as I2C master to Arduino Uno as I2C slave

The Raspberries (all versions) have a hardware-bug in the i2c controllers. The bug being that the rPi cannot correctly handle clock-stretching. See for instance: http://elinux.org/BCM2835_datasheet_errata#p35_I2C_clock_stretching . Your problem looks very much like that bug. There is no work-around ...
by AlfredJingle
Sat Jan 06, 2018 3:39 pm
Forum: Bare metal, Assembly language
Topic: Enabling MMU slows down VFP?
Replies: 5
Views: 744

Re: Enabling MMU slows down VFP?

Hi, I assume that you use a rpi3 (seeing the 1200Mhz). So I tested your little loop (but not unrolled) directly in assembly on my own system (baremetal rpi3 @ 1200Mhz with a corefreq @ 400Mhz), with switched-on MMU, and measured the loop at 334 microsecs. So the same as you in your first test. Hopef...

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