No, all RP2040s are identical, and the bootloader is etched permanently into the chip. Generally not too confusing as you're only programming one board at a time (or at least that is all my brain can manage)

Never thought to try this, but yes your mental model is correct as far as I know

This gives me a blinky light:

I'd like to think in a small company like RPT that the hardware group do ask for opinions on hardware choices from the software people and don't just throw the finished design over the wall and say "program that". One thing we do that is quite unusual is we force hardware engineers to wri...

Also on page 325 is the same example code twice and without any identifier like "example x.yz" (which would allow the text to refer to it twice without it appearing twice) Good point, doesn't flow well and as you say causes unnecessary confusion. Will caption the first instance and replac...

But that doesn't really make sense. I would want as follows: wait for TX FIFO data assert a 0 on TX line (start bit) shift out data assert a 1 on TX line (stop bit) Why would I use IFEMPTY for that instead of BLOCK? Well the short answer is that I hadn't used that particular side set trick when I w...

You could write a PIO program like this: .program measure_pulse mov x, ~null wait 1, pin 0 loop: jmp x-- next next: jmp pin loop mov isr, ~x push (note this is a sketch, I haven't tried this). This would measure the width of every pulse it sees, with a resolution of 2 clock cycles (2 x 8 ns for defa...

As far as I can see the visible ISA is just the tip of the iceberg as far as the complexity of the CPU is concerned. ISA and microarchitecture are separate, but ISA has significant impact on how cheaply and effectively you can implement the microarchitectural features you mentioned. For example, pa...

I have no idea why 'ld' got terminated; I had just left it running. It's eaten up 5.6GB since starting but plenty free. Out of memory ? I don't know. Another one to add to the ever growing 'didn't work' list. Does anyone have instructions for building any RISC-V compiler on a Pi 3B which they know ...

SMI has a 6 bit "address" bus (SA0 to SA5), which I think is misnamed. These pins idle high in between transactions, and seem to be useful mainly for enables, not addresses. This is what they are used for in the SMI NAND driver, which is a small shim sitting between Linux's MTD (NAND) stac...

Thought I'd reply to this old thread as it is the first result on google, so other people may come here too, looking for info. There is now an SMI driver -- see these commits: https://github.com/raspberrypi/linux/commit/e19c303e7d54d986e0bd3e47107a83e30329c1d0 https://github.com/raspberrypi/linux/co...

No, the minimum for GPU memory is 16. The GPU is responsible for some initial setup.

As an alternative to running as root, you can consider adding your username to the group "bluetooth" to get the required permissions.

e.g.
For username "pi".

Thank you Phil! I think I pulled the file from the 4.0 repo a couple of weeks ago.

Sorry for resurrecting an old thread, but I thought it would be useful to add some information. SDIO is supported by the mmc (SD1) driver. In order to use SD1 for SDIO, you'll need to use SD0 (sdhost) for booting, as SD1 is currently being used for this. Phil has written a device tree overlay which ...