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by vsiles
Fri Sep 16, 2016 3:09 pm
Forum: Bare metal, Assembly language
Topic: Trying Bare Metal on Raspberry Pi 2
Replies: 98
Views: 35470

Re: Trying Bare Metal on Raspberry Pi 2

yes, the A7 has a L2 cache / SCU so there is automatic cache coherency so WB or WT is still cached, so there is a coherency. You only have to clean/flush when you enable/disable cache, or work with some device outside the cores, like DMA. If you only want to share data between the cores, the L2 cach...
by vsiles
Fri Sep 16, 2016 5:38 am
Forum: Bare metal, Assembly language
Topic: Trying Bare Metal on Raspberry Pi 2
Replies: 98
Views: 35470

Re: Trying Bare Metal on Raspberry Pi 2

If you want to implement synchronization between cores, you should try to find a simple implementation of spinlock (e.g. Linux) to do things right. Volatile doesn't mean that. Volatile tells the compiler that the variable might be modified by an external source it doesn't know about, so it won't mak...
by vsiles
Thu Sep 15, 2016 5:41 am
Forum: Bare metal, Assembly language
Topic: Trying Bare Metal on Raspberry Pi 2
Replies: 98
Views: 35470

Re: Trying Bare Metal on Raspberry Pi 2

The registers SCTLR, TTBR0, TTBR1, TTBRN, ACTLR are all "per core registers" so you have to perform the initialization procedure (don't forget to invalidate the I/D cache & TLB before enabling them) on each core. However if you want to, you can point the TTBRx to the same tables on each core, sharin...
by vsiles
Wed Sep 14, 2016 5:35 am
Forum: Bare metal, Assembly language
Topic: Trying Bare Metal on Raspberry Pi 2
Replies: 98
Views: 35470

Re: Trying Bare Metal on Raspberry Pi 2

Quick reply which needs more work but don't have much time:
- yes you have one MMU per core
- if at some point you need to "share" data between a core with MMU on and a core with MMU off, don't forget to clean the caches first
- don't forget to set the ACTLR.SMP bit to activate cache coherency
by vsiles
Fri Mar 04, 2016 7:40 pm
Forum: Bare metal, Assembly language
Topic: RPi 3 SMMU setup documentation
Replies: 4
Views: 1311

Re: RPi 3 SMMU setup documentation

I recall reading (on the comments of the announce I think) that this is unchanged and that is the reason why it is still only 1Gb
by vsiles
Fri Mar 04, 2016 3:57 pm
Forum: Bare metal, Assembly language
Topic: Rpi 2/3 irq
Replies: 3
Views: 1576

Re: Rpi 2/3 irq

I'm not sure I got it right. Using this registre, can I: - route 2 special irqs named GPU irq/fiq to a single core only - route all peripheral irq (like sp804) to a single core In both case, I can route every thing to one core only, I can't dispatch per core. If anyone can provider a better/correct ...
by vsiles
Thu Mar 03, 2016 8:50 pm
Forum: Bare metal, Assembly language
Topic: Rpi 2/3 irq
Replies: 3
Views: 1576

Rpi 2/3 irq

Hi ! From what I gathered, neither pi2 nor pi3 has a gic. 1) anybody knows why ? This is really a shame (and a pain, gic is cool) 2) I can't find anywhere in the doc how to choose to which core I want my interrupts délibérés (like timer sp804's irq , not ppi/mailboxes). Is it even possible or do I h...
by vsiles
Mon Feb 01, 2016 8:18 am
Forum: Bare metal, Assembly language
Topic: Trustzone. Boot in secure mode? non-secure mode?
Replies: 5
Views: 2781

Re: Trustzone. Boot in secure mode? non-secure mode?

With the current firmware, the Rpi2 boots in HYP Non Secure mode (only 1 core running, the other are sleeping until you wake them). If you add the kernel_old=1 line to config.txt, the Rpi2 boots in Secure SVC mode (4 cores running). Be advised that the firmware code that goes from Secure SVC to HYP ...
by vsiles
Fri Jan 22, 2016 10:05 am
Forum: Bare metal, Assembly language
Topic: Performance issue
Replies: 10
Views: 2101

Re: Performance issue

I also noticed that Cache/Shareability flags you put in the TTBR0 register have a huge impact on performance !
by vsiles
Thu Jan 21, 2016 11:08 am
Forum: Bare metal, Assembly language
Topic: Performance issue
Replies: 10
Views: 2101

Re: Performance issue

I'm sorry, I forgot to say that I'm on a Rpi2, so the situation is a bit difference with the cortex-a7, and you have to correctly setup the Inner/Outer Shareability domains, but L1 cache should still be one.
by vsiles
Tue Jan 19, 2016 4:32 pm
Forum: Bare metal, Assembly language
Topic: Performance issue
Replies: 10
Views: 2101

Re: Performance issue

Shame on me...
Next time, I'll remove the -O0 right away, this really is a performance killer. In memset the generated code was performing way to much store (mostly to the stack to save local variable all the time)...

My bad :D
by vsiles
Tue Jan 19, 2016 2:55 pm
Forum: Bare metal, Assembly language
Topic: Performance issue
Replies: 10
Views: 2101

Re: Performance issue

I'm pretty sure on raspbian the copy is done since it ouputs the correct value computed after the copy. I'm still going through all the info from the thread hldswrth mentioned, and I see there are lots of ways to improve my code. Thanks for the input !
by vsiles
Fri Jan 15, 2016 12:04 pm
Forum: Bare metal, Assembly language
Topic: Performance issue
Replies: 10
Views: 2101

Re: Performance issue

Thank you for the link, I'll have a look right away !
by vsiles
Fri Jan 15, 2016 10:29 am
Forum: Bare metal, Assembly language
Topic: Performance issue
Replies: 10
Views: 2101

Re: Performance issue

Here are the details: - The MMU and SCTLR.{C,I,Z} are on (D-Cache, I-Cache, Branch prediction). - I also set SCTLR.TRE and SCTLR.AFE for Tex Remapping & simplified model for access flag. - My MMU maps the memory as section, with the S bit set in the mappings - PRRR values are set to Normal Memory, S...
by vsiles
Thu Jan 14, 2016 6:43 pm
Forum: Bare metal, Assembly language
Topic: Performance issue
Replies: 10
Views: 2101

Performance issue

Hi ! Now that I have a small OS that works, I'm looking at (very simple) example to test my system. I'm starting pure baremetal again, no OS, with a simple program that fill 600 4ko pages with random stuff, copy them with a simple for loop in a second buffer, then print a checksum of the second buff...
by vsiles
Wed Dec 30, 2015 11:00 am
Forum: Linux Kernel
Topic: Freeze on wfi when not using FIQ
Replies: 1
Views: 1121

Freeze on wfi when not using FIQ

Hi guys, I'm working on a small secure OS to put in the secure/trustzone world alongside Raspbian. In a few words, what I do to achieve this is: * I removed the USB FIQ using the following line with u-boot: setenv bootargs "dwc_otg.fiq_enable=0 dwc_otg.fiq_fsm_enable=0 mem=768M dwc_otg.lpm_enable=0 ...
by vsiles
Tue Dec 29, 2015 8:11 am
Forum: Bare metal, Assembly language
Topic: Start bare metal programs using u-boot
Replies: 7
Views: 4519

Re: Start bare metal programs using u-boot

As I said, the location where you load the binary should match the entry point of your program. If u-boot's ${kernel_addr_r} is 0x01000000 you should dhcp 0x01000000 foo.bin && go 0x01000000, with a link script that links your binary to start at 0x01000000. If everything works fine when you replace ...
by vsiles
Mon Dec 28, 2015 4:49 pm
Forum: Bare metal, Assembly language
Topic: Start bare metal programs using u-boot
Replies: 7
Views: 4519

Re: Start bare metal programs using u-boot

I'm thinking that you're issue is not on how to "post process" elf files but rather how to create them in the first place. When you ask u-boot to "dhcp 0x8000 foo.bin && go 0x8000" (I'll assume that you have compiled u-boot with the standard rpi config so ${kernel_addr_r} is also 0x8000) it will: - ...
by vsiles
Mon Dec 28, 2015 1:03 pm
Forum: Bare metal, Assembly language
Topic: Start bare metal programs using u-boot
Replies: 7
Views: 4519

Re: Start bare metal programs using u-boot

I don't have any problem to load my code using u-boot (by the way, you can use the mainstream uboot now, they can properly deal with rpi/rpi2). I noticed that you tried to "go 0x8000" but you created your .img using "mkimage -e 0x8040". Which is your binary entry point ? I always link my kernel with...
by vsiles
Wed Dec 16, 2015 8:12 am
Forum: Bare metal, Assembly language
Topic: Trying Bare Metal on Raspberry Pi 2
Replies: 98
Views: 35470

Re: Trying Bare Metal on Raspberry Pi 2

By the way, I recently checked the new firmware and found out that we now start in HYP mode (yes I'm a bit late on this one...)
Does anyone knows if it is the only difference ? Is the new "bootcode" (the one we can replace using kernel_old option) available somewhere ?

Best,
V.
by vsiles
Mon Aug 24, 2015 2:01 pm
Forum: Bare metal, Assembly language
Topic: Status of QEMU emulation of the RPI2
Replies: 0
Views: 559

Status of QEMU emulation of the RPI2

Hi guys,
I've crawled a bit and I can't find any clear information about a qemu target for the rpi2 ?
Does any one know if such a project is available ?

Best,
V.
by vsiles
Mon Apr 20, 2015 10:12 am
Forum: Bare metal, Assembly language
Topic: Accessing SCR in Monitor mode (Pi 2)
Replies: 7
Views: 4068

Re: Accessing SCR in Monitor mode (Pi 2)

At the moment I run my baremetal hobby OS, and we are not yet to the "both secure & normal world" things, but we aim to run android/ubuntu on the normal world... one day ;)
by vsiles
Thu Apr 16, 2015 9:37 am
Forum: Bare metal, Assembly language
Topic: Accessing SCR in Monitor mode (Pi 2)
Replies: 7
Views: 4068

Re: Accessing SCR in Monitor mode (Pi 2)

Hi, since Stephen Warren is working on fixing rpi2 usb/ethernet support in u-boot, I switched from my boot code to using u-boot, which already supports secure boot. To boot in secure mode with u-boot, I needed to fix a couple of places in u-boot, but very little was actually necessary, it is mainly ...
by vsiles
Mon Apr 13, 2015 3:35 pm
Forum: Bare metal, Assembly language
Topic: u-boot and ethernet on Raspberry 2
Replies: 5
Views: 3035

Re: u-boot and ethernet on Raspberry 2

A collegue of mine managed to clone Stephen's github in a state where usb/ethernet is actually working ! But the current head of the repository seems to fail for another (new) reason. I'll wait until Stephen has finished his work.
Thanks for the reminder !

V.
by vsiles
Wed Apr 08, 2015 10:14 am
Forum: Bare metal, Assembly language
Topic: u-boot and ethernet on Raspberry 2
Replies: 5
Views: 3035

Re: u-boot and ethernet on Raspberry 2

Any one got news about ethernet support for rpi 2 in u-boot ?

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