Search found 86 matches
- Fri Jan 17, 2020 5:09 pm
- Forum: Bare metal, Assembly language
- Topic: Mini UART
- Replies: 9
- Views: 1167
Re: Mini UART
Hello, Are you sure that your "printf" routine is not doing some buffering, internally, in order to print full lines? Such buffering may make sense if you're in a preemptive environment (which you are not). Check the implementation of printf. If printf is buffering internally, then the way...
- Thu Jan 16, 2020 8:28 pm
- Forum: Bare metal, Assembly language
- Topic: Support for audio in the USB driver?
- Replies: 1
- Views: 725
Support for audio in the USB driver?
Hello, I've looked into several bare metal USB drivers (Circle, USPI, CSUD) and I can find no support for audio beyond MIDI. Has someone worked on things like reading data from a USB microphone and possibly pushing sound to USB speakers? If such a driver does not exist, could this document allow me ...
- Thu Jan 16, 2020 7:50 pm
- Forum: Bare metal, Assembly language
- Topic: AArch64: calling EL0 function from EL1
- Replies: 2
- Views: 711
Re: AArch64: calling EL0 function from EL1
Thanks Schnoogle, I wanted to be sure.
Best,
Dpotop
Best,
Dpotop
- Mon Jan 13, 2020 4:42 pm
- Forum: Bare metal, Assembly language
- Topic: AArch64: calling EL0 function from EL1
- Replies: 2
- Views: 711
AArch64: calling EL0 function from EL1
Hello,
I'd like for privileged (EL1) code to call an unprivileged (EL0) function, and
then get control back to EL1. Is there a simple way of doing it, which does not
involve context saving and SVC instructions?
Best,
Dumitru
I'd like for privileged (EL1) code to call an unprivileged (EL0) function, and
then get control back to EL1. Is there a simple way of doing it, which does not
involve context saving and SVC instructions?
Best,
Dumitru
- Fri Dec 20, 2019 2:48 pm
- Forum: Bare metal, Assembly language
- Topic: Looking for file DWC_otg_databook.pdf
- Replies: 0
- Views: 528
Looking for file DWC_otg_databook.pdf
Hello, I.m looking for the old USB chip documentation DWC_otg_databook.pdf . In the documentation for BCM2835 tehy say it can be downloaded from Synopsys, but it seems Synopsys changed the access rules: you have to have an account, and to have an account you have to provide a "site number"...
- Sun Dec 15, 2019 2:48 pm
- Forum: Bare metal, Assembly language
- Topic: Circle - C++ bare metal environment (with USB)
- Replies: 317
- Views: 99231
Re: Circle - C++ bare metal environment (with USB)
Hello, First of all, I'd like to thank all contributors for this library. It's the first time I look into it, and it looks very clean. I even pushed optimization to -O3 and the code still works! I'm considering using it as a basis for my future bare metal work (I'm currently re-coding everything sta...
- Mon Dec 09, 2019 12:45 pm
- Forum: Bare metal, Assembly language
- Topic: RPi4 vs. RPi3
- Replies: 2
- Views: 794
RPi4 vs. RPi3
Hello, I wrote a small multi-threaded application on the RPi3, and I consider porting it to RPi4. Could you point me to the differences and difficulties I should expect ? I guess they will be related to differences between: 1. the Cortex A53 and Cortex A72 2. the memory organization (1Go vs 4Go) 3. ...
- Mon Dec 09, 2019 10:57 am
- Forum: Bare metal, Assembly language
- Topic: Circle - C++ bare metal environment (with USB)
- Replies: 317
- Views: 99231
RPi4 and USB3 performance questions
Hello, I'm considering interfacing with a high-speed device in bare metal on the RPi4. Circle seems to be the only bare metal library currently doing RPi4 and USB. However, I'd need more than that (and of course I'm quite willing to program it). I'd like to have your opinion on the feasibility of th...
- Sun Oct 06, 2019 10:08 am
- Forum: Bare metal, Assembly language
- Topic: Boot changes on Raspberry Pi 1 B+ ?
- Replies: 1
- Views: 1536
Re: Boot changes on Raspberry Pi 1 B+ ?
I found a workaround - creating a new SD card based on Raspbian Buster.
But this does not answer my previous question - what changed in the
RPI, while on the outside it's labeled in the same way.
Unsettling, when you use the cards for teaching.
Best,
Dpotop
But this does not answer my previous question - what changed in the
RPI, while on the outside it's labeled in the same way.
Unsettling, when you use the cards for teaching.
Best,
Dpotop
- Sun Oct 06, 2019 8:53 am
- Forum: Bare metal, Assembly language
- Topic: Boot changes on Raspberry Pi 1 B+ ?
- Replies: 1
- Views: 1536
Boot changes on Raspberry Pi 1 B+ ?
Hello, I'm teaching using Raspberry Pi 1 B+ cards and bare metal software. I've just got a new batch of Raspberry Pi B+ cards, which should be identical to those I already have. At least, they have the same markings: B+, V1.2, 2014. However, they will NOT boot using the same SW I use on the old ones...
- Thu Apr 18, 2019 8:58 am
- Forum: Bare metal, Assembly language
- Topic: Best way to synchronize timers?
- Replies: 1
- Views: 651
Best way to synchronize timers?
Hello, I'd like to execute code periodically on all cores. For instance, I'd like to launch every 10ms computations on all cores. These computations must start at the same time (as synchronized as possible). I look for the best way to do it. What I currently have is one timer (the "local timer&...
- Tue Mar 12, 2019 9:07 am
- Forum: Bare metal, Assembly language
- Topic: Coherency when starting in EL3
- Replies: 3
- Views: 981
Re: Coherency when starting in EL3
Thanks LdB,
I had completely overlooked the Cortex-A53-specifics.
Is register CPUECTLR_EL1 the only one I should be concerned
with? Are there other registers of interest?
In the manual I see there are lots of "implementation-defined"
registers besides this one.
Regards,
Dumitru
I had completely overlooked the Cortex-A53-specifics.
Is register CPUECTLR_EL1 the only one I should be concerned
with? Are there other registers of interest?
In the manual I see there are lots of "implementation-defined"
registers besides this one.
Regards,
Dumitru
- Mon Mar 11, 2019 10:09 pm
- Forum: Bare metal, Assembly language
- Topic: Coherency when starting in EL3
- Replies: 3
- Views: 981
Coherency when starting in EL3
Hello, I have a weird problem - when booting in EL3 I can't seem to be able to enable coherency between cores. I have two boot settings: - in the first I boot in EL2 (classical) - in the second I boot in EL3 In both cases, the configuration for EL2 and EL1 is exactly the same, both for MMU and for p...
- Wed Feb 27, 2019 8:04 pm
- Forum: Bare metal, Assembly language
- Topic: MMU config of RPi3 - problem with ARMv8 ARM
- Replies: 10
- Views: 1569
Re: MMU config of RPi3 - problem with ARMv8 ARM
Ok, so with your help (thank you again) I start to understand more of the ARM documents, and contribute productively to this discussion. I'm now looking into the "Programmer’s Guide for ARMv8-A", which can be found here: http://infocenter.arm.com/help/topic/com.arm.doc.den0024a/DEN0024A_v8...
- Wed Feb 27, 2019 4:49 pm
- Forum: Bare metal, Assembly language
- Topic: MMU config of RPi3 - problem with ARMv8 ARM
- Replies: 10
- Views: 1569
Re: MMU config of RPi3 - problem with ARMv8 ARM
No, with 64k granularity pages are on a 64k boundary (by definition). VA[47:29] is used as an index in the level 2 lookup (if used) to give the address of the level 3 table, VA[28:16] is used as an index in the level 3 lookup to give you PA[47:16], VA[15:0] gives you PA[15:0] directly. I guess the ...
- Wed Feb 27, 2019 1:15 pm
- Forum: Bare metal, Assembly language
- Topic: MMU config of RPi3 - problem with ARMv8 ARM
- Replies: 10
- Views: 1569
Re: MMU config of RPi3 - problem with ARMv8 ARM
2. If T0SZ=39, I am again at L3, VAs have 25 bits. Then, bits [11:0] are always taken unchanged from the VA, and bits [24:12] are taken from the page descriptor. Right ? With 64K granularity then PA[15:0] = VA[15:0] Ok, but then, in the case mentioned above, the pages pointed to by two successive d...
- Wed Feb 27, 2019 11:58 am
- Forum: Bare metal, Assembly language
- Topic: MMU config of RPi3 - problem with ARMv8 ARM
- Replies: 10
- Views: 1569
Re: MMU config of RPi3 - problem with ARMv8 ARM
The DDI0487 document on page D5-2419 has a nice comparision table D5-13, called "TnSZ values for and input address rangesa for starting at this level" which compares possible values, and tells you the initial lookup level. In short, with 16k pages if you want to start at translation level...
- Wed Feb 27, 2019 7:28 am
- Forum: Bare metal, Assembly language
- Topic: MMU config of RPi3 - problem with ARMv8 ARM
- Replies: 10
- Views: 1569
Re: MMU config of RPi3 - problem with ARMv8 ARM
Diagram D5-15 is for level 0, 1 & 2 descriptor formats, the level 3 page descriptor format is diagram D5-17 on page 2448. Excellent, thanks a lot! Can you also point me to the place where they explain how the initial translation level is chosen for Stage 1 translation? I only found a way to set...
- Tue Feb 26, 2019 4:56 pm
- Forum: Bare metal, Assembly language
- Topic: MMU config of RPi3 - problem with ARMv8 ARM
- Replies: 10
- Views: 1569
MMU config of RPi3 - problem with ARMv8 ARM
Hello, I try to reconfigure the MMU beyond what is done in the examples of LdB. I try to do this by building upon an example of ARMv8 ARM, which can be found here: https://static.docs.arm.com/ddi0487/da/DDI0487D_a_armv8_arm.pdf The example is the one in section K7.1.2, fig. K7-11, page 7293. I find ...
- Thu Feb 21, 2019 7:02 am
- Forum: Bare metal, Assembly language
- Topic: Taking an exception disables interrupts?
- Replies: 2
- Views: 1324
Re: Taking an exception disables interrupts?
Thanks a lot LdB - the first paragraphs in your link contained exactly the information I looked for.
Dpotop
Dpotop
- Wed Feb 20, 2019 11:15 pm
- Forum: Bare metal, Assembly language
- Topic: Taking an exception disables interrupts?
- Replies: 2
- Views: 1324
Taking an exception disables interrupts?
Hello,
There's a point I can't find the reference in the ARMv8 ARM - it's probably
there, but I just can't find it:
When an exception is taken (any type) are interrupts (IRQs and
FIQs) disabled?
Best regards,
Dpotop
There's a point I can't find the reference in the ARMv8 ARM - it's probably
there, but I just can't find it:
When an exception is taken (any type) are interrupts (IRQs and
FIQs) disabled?
Best regards,
Dpotop
- Mon Feb 18, 2019 8:18 pm
- Forum: Bare metal, Assembly language
- Topic: EL switching
- Replies: 7
- Views: 2111
Re: EL switching
Cool !
But is the VideoCore initialized if I boot at address 0?
Will it reply to mailbox requests?
Best,
Dpotop
But is the VideoCore initialized if I boot at address 0?
Will it reply to mailbox requests?
Best,
Dpotop
- Sun Feb 17, 2019 8:39 pm
- Forum: Bare metal, Assembly language
- Topic: EL switching
- Replies: 7
- Views: 2111
Re: EL switching
RPi3 newbie question: I thought RPi3 is at EL2 when control is given to kernel8.img. So, how come you're at EL3?
Dpotop
Dpotop
- Fri Feb 15, 2019 5:06 pm
- Forum: Bare metal, Assembly language
- Topic: RPi3 - start cores and spinlock sync code needed
- Replies: 11
- Views: 2129
Re: RPi3 - start cores and spinlock sync code needed
Dear LdB and bzt,
Thanks a lot, your insight into Linux booting is quite useful!
If the de-compressed Linux kernel can go between 0x8000 and 0x80000,
it also means I can load my code there, isn't it? I'll probably give it a try.
Best regards,
Dpotop
Thanks a lot, your insight into Linux booting is quite useful!
If the de-compressed Linux kernel can go between 0x8000 and 0x80000,
it also means I can load my code there, isn't it? I'll probably give it a try.
Best regards,
Dpotop
- Fri Feb 15, 2019 3:16 pm
- Forum: Bare metal, Assembly language
- Topic: Question on mailboxes on RPI3
- Replies: 0
- Views: 775
Question on mailboxes on RPI3
Hello, I want to be sure about some details before starting to code some interrupt-related stuff. Can you please tell me if the following assumptions I make are correct? Even partial answers will help me. 1. The RPI3 inherits most of the memory-mapped SoC peripherals of the RPi1, with the difference...