Raspberry Pi Forums

Akane

Cannot give any schedules, Japan is a particularly long winded process requiring lots of documentation changes plus changes to the silk screening on the board. Check out Roger's blog post on the subject. https://www.raspberrypi.org/blog/compliance-and-why-raspberry-pi-4-may-not-be-available-in-your...

Akane

So now we have an electromagnetic anechoic box from Micronix, and we are writing GPGPU library for VideoCore VI: https://github.com/Idein/py-videocore6 . It's working very well with simple loops e.g. https://github.com/Idein/py-videocore6/blob/master/tests/test_qpu.py and should work with more compl...

Akane

OK, so it appears that the VideoCore6 specifications are not publicly available, so I am afraid I cannot comment on your question with regard to the instructions. You may be able to glean something from the publicly available Mesa driver. I've read the Mesa code many times, only to find that Mesa d...

Akane

Thanks. I see.

Akane

@jamesh We are trying to create py-videocore6, an easy programming environment for VideoCore VI QPU, like the one for VideoCore IV QPU https://github.com/nineties/py-videocore . For now, we have difficulty in using VPM and its DMA. Do you know what values to be fed to the vpmsetup instruction for DM...

Akane

No, nope. The correct theoretical performance of the GPUs is as follows: VideoCore IV @ 250MHz: 250 [MHz] x 3 [slice] x 4 [qpu/slice] x 4 [processor] x 2 [op/clock] = 24 Gflop/s VideoCore IV @ 300MHz: 300 [MHz] x 3 [slice] x 4 [qpu/slice] x 4 [processor] x 2 [op/clock] = 28.8 Gflop/s VideoCore VI @...

Akane

TonySterrett wrote: ↑
Wed Sep 18, 2019 12:55 pm

Akane wrote: ↑
Wed Sep 18, 2019 12:33 am
offset should be 0xFE000000?
Yes this is the base address for the Pi 4

The log shows that

Code: Select all

mapmem: offset = 0

which indicates that the offset is mistakenly set to 0 instead of 0xFE000000 I suspect.

Akane

offset should be 0xFE000000?

Akane

No, nope. The correct theoretical performance of the GPUs is as follows: VideoCore IV @ 250MHz: 250 [MHz] x 3 [slice] x 4 [qpu/slice] x 4 [processor] x 2 [op/clock] = 24 Gflop/s VideoCore IV @ 300MHz: 300 [MHz] x 3 [slice] x 4 [qpu/slice] x 4 [processor] x 2 [op/clock] = 28.8 Gflop/s VideoCore VI @ ...

Akane

Dom, who is an engineer at Pi Towers, said QPU cannot access the peripheral bus: viewtopic.php?f=72&t=128309. So it's unlikely I think.

Akane

It's great to hear that you are doing well. Please continue rocking!

(And sorry for my mistakes in English!)

Akane

Thanks for the quick answer, The address can be different across QPU threads, that is, you can read up to 16 x 4bytes of memory on a TMU read. Are the 16 * 4 Bytes the 16 SIMD-elements times 4 Bytes data-type? If so, what does this have to do with threads? Or has the TMU a cache of 16 requests Yes ...

Akane

For random accesses, I recommend to use TMU because it's more flexible than VPM DMA. To do TMU read, you do: 1. Write memory address (aligned with 4 byte) to TMU[01]_S. The address can be different across QPU threads, that is, you can read up to 16 x 4bytes of memory on a TMU read. 2. Signal the TMU...

Akane

Thank you for your reply! You are correct! Eventually I noticed that I must use non-bufferable memory for DMA operation since L2C on the ARM is speculative. i.e. We cannot know when the memory is fetched if it's being mapped. I changed the flow to unmap the memory instead of (3) and re-map it instea...

Akane

I'm using this code https://github.com/Terminus-IMRC/qmkl/blob/master/src/memory.c#L111 for memory allocation, which is almost the same flow as hello_fft. However, instead of mapping memory on /dev/mem, I'm using /dev/vc-mem to change vma->vm_page_prot: https://github.com/Idein/linux/blob/rpi-4.9.y-...

Akane

Thank you for your reply! You need to be careful when specifying "L2". The V3D has a unified L2 cache for pixel data and QPU instructions but there is also a system-level L2 cache. So Raspberry Pi 2&3 have three L2 caches (V3D unified, V3D system-level and ARM unified) ? Whether memory operations ge...

Akane

Hello. I'm finding a way to fix this L2 cache-related problem. Here, let "mapped memory" be a memory which is allocated through the Mailbox interface and mmap()'ed on /dev/mem. And let "normal memory" be a memory which is allocated by using malloc(). I noticed that accessing mapped memory is relativ...

Akane

I see... so complicated pipelines... I hope it can be done!

Thank you very much for developing Raspberry Pi stuffs so hard! You are a great!

Akane

@6by9 Hi. I want to ask you: Is it possible to convert bayer format such as BAYER_SBGGR10P to other format by using MMAL? Does vc.ril.isp have an ability to do this? EDIT: If I set MMAL_ENCODING_BAYER_SBGGR10P to vc.ril.isp's input encoding field, mmal doesn't say error. So I thought isp can consume...

Akane

According to the manual, there seems be no way to set the semaphore counters.
However, there is another way to reset the counters: disabling and re-enabling QPU by using Mailbox call.

Akane

Wow. Thanks. 1.) To my understanding, I can replicate a non-literal value among all elements (in a quad/the whole SIMD) by writing it into the r5 accumulator (from quad/SIMD-element 0) and reading it again. Is this correct? Yes. If you write to r5 on ra, values are distributed in quads (from [4i] to...

Akane

I mean 0x20>>1=0x10, 0xc8>>1=0x64 and 0x18>>1=0x0c. Sorry.

And, ah, I see that there is a crypt module on CMv2 and the reason. I'm sad of this. Thank you.

Akane

Hello. I made my own camera module for RPi. It uses IMX219, but this is not the same as one on the official RPi camera module v2. While I2C addresses of IMX219 and its VCM driver on the official one are 0x20 and 0xc8 , those of mine are 0x20 and 0x18 . So currently I'm unable to use my own camera mo...

Akane

Don't hesitate to ask me ;) I haven't tested QPU threads before, but I think "threadable" flag can only be set through GL/NV/VG shader records on control list (Table 45-47 and control list code=64-67). FYI, control list is a sequence of instructions for OpenGL ES and so on. Accumulators and conditio...

Akane

2.2) You cannot read directly from RAM through VPM. To read the content of RAM, you must issue DMA load explicitly from RAM to VPM. By "issue DMA load explicitly", do you mean setting up DMA and writing an address to the VPM_LD_ADDR register? Yes. For 2.4, I went with something like xor.set_flags N...

Search found 50 matches

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