More on the beta boards

As promised, here’s some more info on the red wire visible in Dom’s video from last week.

When we first got the boards back from the factory, the core power supply for the SoC wasn’t working; this 1.2V supply drives all of the core logic in the device, and is generated directly from the 5V input via an integrated switch-mode power supply. A bit more investigation revealed that the 19.2MHz system clock wasn’t running, and after a bit of digging around we found that this was because its power supply balls weren’t connected to the system 1.8V supply. The red wire is there to bring in power to these balls.

The mistake turns out to have been in the original schematics for the board, rather than in the translation to the PCB. At several points in the schematics we have structures that look a bit like this:

Here, the SDC_VDD rail is generated by an on-chip LDO, decoupled by three external capacitors, and then pushed back into four balls. The offending bit of the schematic looks like this:

At first glance, this looks like the same structure, but in fact all eight pins are inputs, and the SDRAM_1V8 rail, which should be tied to the system 1.8V supply, ends up floating. Fortunately a small change to the PCB layout fixes this problem; the other beta boards have been fixed by carefully removing an area of solder mask and applying a blob of solder.

Thanks to Paul Grant at Broadcom for his help in tracking this one down.