GPIO Current limits?


3 posts
by rurwin » Tue Feb 21, 2012 7:45 am
There's a nice datasheet with all the register details on, but the one thing it does not have on there is the voltage and current limits for the GPIO pins.

We need to know how much current the SoC can source and sink, and what voltages it puts out, if we are to build effective buffers and level shifters. Failing that, which logic families is it compatible with, what is its fan-out and how many input unit loads does it represent?
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by TonyD » Tue Feb 21, 2012 1:17 pm
I wouldn't expect the SoC is able to source or sink too much current, guessing I would say somewhere between 5 and 10mA per pin.
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by Gert van Loo » Tue Feb 21, 2012 1:20 pm
I posted a long email about GPIO current a while ago.  I suggested to limit it to ~5mA/pin. In practice you just have to know what you are doing, drawing a lot of current from one pin or a bit from a lot of pins. It is all a matter of voltage droop/ground bounce, rise/fall times, capacitive loads, frequency, signal quality etc.

It is CMOS logic running at 3V3.
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